Add syntax highlighting for Verilog, SystemVerilog, and VHDL

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    • Type: Suggestion
    • Resolution: Won't Fix
    • None
    • Component/s: None
    • None

      (U) For crucible code reviews, it would be nice to have syntax highlighting for verilog, systemverilog and VHDL source code files.

        1. verilog.def
          4 kB
        2. vhdl.def
          3 kB

            Assignee:
            Unassigned
            Reporter:
            Michael Hilton
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              Created:
              Updated:
              Resolved: